[新聞](Feb 17, 2005)物理：縱橫閂（crossbar latch）--下一代納米電路器件?

惠普公司的研究人員在最近的一期應用物理雜誌（Journal of Applied Physics）宣稱，他們提出並證明了一種稱為”縱橫閂（crossbar latch）” 的納米級別的器件新技術可以取代電晶體（transistor），正如上個世紀中葉電晶體取代真空管（vacuum tube）一樣，成為電子行業下一代核心基礎器件。可編程的縱橫電路一直是納米級電子電路的關鍵結構之一。 但為了強調製作的可行性，大部分縱橫電路設計都基於二維器件。這樣一來，信號的存儲和反轉成了縱橫電路的兩個突出的弱點。在這篇題為“縱橫閂（Crossbar latch）： 縱橫電路中的邏輯值存儲，恢復與反轉”的論文中，來自惠普實驗室量子科學小組（Quantum Science Research Group）的Philip J. Kuekes, Duncan R. Stewart, 和R. Stanley Williams 共同提出了一個完整的解決方案。這種器件可以在信號線上存儲邏輯值，並能恢復和反轉該值。該閂（latch）由穿插著兩根控制線的單根信號線構成。控制線與信號線之間由分子節開關連接。通過控制線加入一系列脈衝電壓，並使分子開關轉向相反極，閂（latch）可以執行“非（NOT）”操作。相應地，也可以執行“與（AND）”和“或（OR）”操作。結合電阻和二極體邏輯門，這三項操作原則上使得所有基於縱橫電路，甚至其他納米級別的積體電路的廣義計算成為可能。通過在絕緣襯底上依次沉積底層電極（100納米厚的鉑），Langmuir－Blodgett（LB）單層（C17H35COOH分子）和頂層電極（5納米厚的鈦和200納米厚的鋁），研究人員在實驗室實現了這種器件。結合惠普實驗室以前的研究成果，研究人員有信心很快完成實用的納米級電路。

原始論文JOURNAL OF APPLIED PHYSICS 97, 034301 (2005) The crossbar latch: Logic value storage, restoration, and inversion in crossbar circuits

相關的講義(原文)

http://www.wellesley.edu/CS/courses/CS331/notes/notes_networks.pdf

可從第三章開始看
chapter3: Mesh
chapter4: Tree
chapter6: Hypercube

Hypercube Connection ( Binary n-Cube )

Hypercube networks consist of N = 2^k nodes arranged in a k dimensional hypercube.The nodes are numbered 0 , 1, ....2^k -1 and two nodes are connected if their binary labels differ by exactly one bit.




























K dimensional hypercube is formed by combining two k-1 dimensional hypercubes and connecting corresponding nodes i.e. hypercubes are recursive.each node is connected to k other nodes i.e. each is of degree k
The departmental NCUBE is based on this topology i.e. a 5 dimensional hypercube (64 nodes)

Rings

A simple ring is just a linear array with the end nodes linked.







It is equivalent to a 1D mesh with wraparound connections. One drawback to this network is that some data transfers may require N/2 links to be traversed e.g. A and B above ( 3 ).
This can be reduced by using a chordal ring This is a simple ring with cross or chordal links between nodes on opposite sides









.

Mesh

In a mesh network, the nodes are arranged in a k dimensional lattice of width w, giving a total of w^k nodes.[ usually k=1 (linear array) or k=2 (2D array) e.g. ICL DAP ]Communication is allowed only between neighbouring nodes. All interior nodes are connected to 2k other nodes.

Topology

The shape of a local-area network (LAN) or other communications system. Topologies are either physical or logical. There are four principal topologies used in LANs.

bus topology:
All devices are connected to a central cable, called the bus or backbone. Bus networks are relatively inexpensive and easy to install for small networks. Ethernet systems use a bus topology.
ring topology :
All devices are connected to one another in the shape of a closed loop, so that each device is connected directly to two other devices, one on either side of it. Ring topologies are relatively expensive and difficult to install, but they offer high bandwidth and can span large distances.
star topology:
All devices are connected to a central hub. Star networks are relatively easy to install and manage, but bottlenecks can occur because all data must pass through the hub.
tree topology:
A tree topology combines characteristics of linear bus and star topologies. It consists of groups of star-configured workstations connected to a linear bus backbone cable.
These topologies can also be mixed. For example, a bus-star network consists of a high-bandwidth bus, called the backbone, which connects a collections of slower-bandwidth star segments.
For network diagrams, see Network Topology Diagrams in the Quick Reference section of Webopedia

網路上關於intercpnnection networks的PPT

http://www.ee.duke.edu/~sorin/prior-courses/ece259-spring2004/lectures/6-interconnect.ppt

這個版本跟上面的有點像，不過是中文的:http://www.csie.nuk.edu.tw/~wuch/course/eef011/4p/eef011-8.pdf


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相關資料:
Interconnection Networks for Parallel Processing Systems
Simulation is inevitable for dimensioning interconnection networks for parallel processing and communication systems. Even if the network topology is simple and highly regular, its size and the needed simulation accuracy result in high performance requirements of the simulator, creating a need for parallel simulation as a means to reduce turnaround times. So far, this research has resulted in the implementation of a parallel time-driven packet-switching and wormhole-routing multistage interconnection network simulator on the MasPar MP-1 SIMD machine and a parallel event-driven wormhole-routing direct network simulator running on the Intel Paragon MIMD machine.